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DM163
Version : A.004 Issue Date : 2005/8/19 File Name : SP-DM163-A.004.doc Total Pages: 21
8x3-CHANNEL CONSTANT CURRENT LED DRIVER
9 7 1
SILICON TOUCH TECHNOLOGY INC.
9-7F-1, Prosperity Road I, Science Based Industrial Park, Hsin-Chu, Taiwan 300, R.O.C. Fax886-3-5645626 Tel886-3-5645656
SILICON TOUCH TECHNOLOGY INC.
DM163
DM163 8x3-CHANNEL CONSTANT CURRENT LED DRIVERS
General Description
The DM163 is a LED driver that comprises shift registers, data latches, 8x3-channel constant current circuitry with current value set by 3 external resistors, and 64 x 256 gray level PWM (Pulse Width Modulation) function unit. Each channel provides a maximum current of 60 mA. The grayscale data are separated into BANK0 and BANK1 respectively, selected by SELBK pin. BANK0 is 6-bits grayscale data and the BNAK1 is 8-bits grayscale data. Depending on the system requirement, both PWM banks could be utilized jointly to achieve maximum 8+6 bit grayscale performance. Alternatively, users can choose either 64-graylevel bank or 256-graylevel bank for dot correction, and the remaining bank as image data. DM163 could also be constructed as a PWM controller for LED drivers. When VDDH is connected to VDD, each of the 24 output channels outputs can act as an inverse digital signal for controlling the LED driver.
Features
24 Output Channels 8 + 6-bits PWM grayscale Control Constant Current Output: 5mA to 60mA LED Power Supply Voltage up to 17V VDD=3V to 5.5V Varied Output Current Level Set By 3 External Resistors Serial Shift-In Architecture for Grayscale Data
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DM163
Block Diagram
Figure 1. Functional Schematic of Whole Chip The schematic of DM163 comprises of several fundamental units as shown in Figure 1. The grayscale data are input onto the DM163 by the SIN pin and transferred according to the synchronous clock DCK. Meanwhile, in order to separate the data into two groups, SELBK is designed as a switch control pin. When a sequence of data is already transferred onto the chip, the LAT_B="H" is set to convey it into the comparator unit. Compared with the counter signals, the grayscale data will determine the PWM control signal to display varied luminance at driver output. The Rext resistors are able to set diverse output current levels. The detailed schematic of each channel is shown as Figure 2.
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DM163
Block Diagram
Figure 2. The Detailed Schematic of Each Channel
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DM163
Pin Connection (Top view) QFP44
Pin No. 1 2 3 4 5 6 7 8 9 10 11
NAME SIN VSS IOUT[0] IOUT[1] IOUT[2] IOUT[3] IOUT[4] IOUT[5] IOUT[6] VSS_DR VSS_DR
Pin No. 12 13 14 15 16 17 18 19 20 21 22
NAME IOUT[7] IOUT[8] IOUT[9] IOUT[10] IOUT[11] IOUT[12] IOUT[13] IOUT[14] IOUT[15] IOUT[16] VSS_DR
Pin No. 23 24 25 26 27 28 29 30 31 32 33
NAME VSS_DR IOUT[17] IOUT[18] IOUT[19] IOUT[20] IOUT[21] IOUT[22] IOUT[23] VDDH[R] VDDH[G] VDDH[B]
Pin No. 34 35 36 37 38 39 40 41 42 43 44
NAME VDD SOUT RST_B EN_B SELBK GCK LAT_B DCK REXT[B] REXT[G] REXT[R]
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DM163
QFN40
Pin No. 1 2 3 4 5 6 7 8 9 10
NAME REXT[R] SIN VSS IOUT[0] IOUT[1] IOUT[2] IOUT[3] IOUT[4] IOUT[5] IOUT[6]
Pin No. 11 12 13 14 15 16 17 18 19 20
NAME IOUT[7] IOUT[8] IOUT[9] IOUT[10] IOUT[11] IOUT[12] IOUT[13] IOUT[14] IOUT[15] IOUT[16]
Pin No. 21 22 23 24 25 26 27 28 29 30
NAME IOUT[17] IOUT[18] IOUT[19] IOUT[20] IOUT[21] IOUT[22] IOUT[23] VDDH[R] VDDH[G] VDDH[B]
Pin No. 31 32 33 34 35 36 37 38 39 40
NAME VDD SOUT RST_B EN_B SELBK GCK LAT_B DCK REXT[B] REXT[G]
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DM163
Pin Description
FUNCTION QFP pin number QFN pin number Output protection pins. 31 28 They could be connected independently 32 29 or to LED supplies (VLED). 33 30 Power supply terminal. 34 31 Ground terminal. 2 3 Driver ground 10, 11, 22, 23 Thermal pad Serial input for grayscale data. 1 2 Serial output for grayscale data. 35 32 Synchronous clock input for serial data 41 38 DCK transfer. The input data of SIN is transferred at rising edges of DCK. If SELBK is H, shift-in date would be 38 35 stored in the 8-bit BANK 1. SELBK If SELBK is L, shift-in date would be stored in the 6-bit BANK 0. When LAT_B converts from H to L, 40 37 LAT_B grayscale data in both shift register banks are latched. GCK Clock input for PWM operation. 39 36 44 1 External resistor connected between REXT and GND for driver current setting. 43 40 REXT(R) controls outputs OUT0, 3, 6, 9, 42 REXT(R) 39 12, 15, 18, 21. REXT(G) REXT(G) controls outputs OUT1, 4, 7, 10, REXT(B) 13, 16, 19, 22. REXT(B) controls outputs OUT2, 5, 8, 11, 14, 17, 20, 23. 3, 4, 5, 6, 7, 8, 9, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15,16, 11, 12, 13, 14, 15, IOUT0~23 LED driver outputs. 17, 18, 19, 20,21, 16, 17, 18, 19, 20, 24, 25, 26, 27,28, 21, 22, 23, 24, 25, 29, 30 26, 27 Input terminal of output enable. All 37 34 EN_B outputs are OFF when EN_B is H. The IC is initialized when RST_B low. 36 33 There is an internal pull-up on this pin. This pin couldn't be floating. Before using RST_B the IC, it must be reset first. If each channel is assigned to drive multiple LEDs, IC should be reset before each LED data latch to prevent from flashing. PIN NAME VDDH (R) VDDH (G) VDDH (B) VDD VSS VSS_DR SIN SOUT
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Maximum Ratings (Ta=25C, Tj(max) = 140C)
CHARACTERISTIC Supply Voltage Input Voltage Output Current Output Voltage DCK Frequency GCK Frequency GND Terminal Current Power Dissipation Thermal Resistance Operating Temperature Storage Temperature SYMBOL VDD VIN IOUT VOUT FDCK FGCK IGND PD Rth(j-a) Top Tstg RATING -0.3 ~ 7.0 -0.3 ~ VDD+0.3 60 -0.3 ~ 17 20 20 1440 1.36 ( QFP44); 3.63 (QFN40) (Ta=25C) 84.42 ( QFP44 ); 31.67 (QFN40) -40 ~ 85 -55 ~ 150 UNIT V V mA V MHz MHz mA W
/W
Recommended Operating Condition
DC Characteristics (Ta = 25C)
CHARACTERISTIC Supply Voltage Output Voltage Output Current SYMBOL VDD VOUT IO IOH IOL VIH VIL CONDITION MIN. 3 TYP. MAX. 5.5 17 60 2 -2 VDD+0.2 0.2 VDD UNIT V V mA

OUTn SERIAL-OUT SERIAL-OUT
5
Input Voltage

0.8 VDD -0.2

V
AC Characteristics (VDD = 5.0 V, Ta = 25C)
CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT
DCK Frequency DCK pulse duration DCK rise/fall time GCK Frequency GCK pulse duration GCK rise/fall time
Set-up Time for SIN Hold Time for SIN Set-up Time for DCK LAT_B Pulse Width Set-up Time for LAT_B Set-up Time for SELBK Hold Time for SELBK
FDCK
twh / twl tr / tf
FGCK
twh / twl tr / tf
tsetup(D) thold(D) tsetup(L) tw LAT Tsetup(G) Tsetup(S) Thold(S)
Cascade operation High or low level High or low level
Before DCK rising edge After DCK rising edge Before LAT_B falling edge
15 1 15
2 3 3 5 13 5 1

20 20 20 20

MHz ns ns MHz ns ns
ns ns ns ns ns ns ns
Before GCK rising edge Before DCK rising edge After DCK rising edge
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AC Characteristics (VDD = 3.3 V, Ta = 25C)
CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT
DCK Frequency DCK pulse duration DCK rise/fall time GCK Frequency GCK pulse duration GCK rise/fall time
RST_B pulse duration Set-up Time for SIN Hold Time for SIN Set-up Time for DCK LAT_B Pulse Width Set-up Time for LAT_B Set-up Time for SELBK Hold Time for SELBK
FDCK
twh / twl tr / tf
FGCK
twh / twl tr / tf
twrst_b tsetup(D) thold(D) tsetup(L) tw LAT Tsetup(G) Tsetup(S) Thold(S)
Cascade operation High or low level Cascade operation High or low level Low level
Before DCK rising edge After DCK rising edge Before LAT_B falling edge
15 1 15
100 2 5 5 7 23 9 1

20 20 20 20

MHz ns ns MHz ns ns
ns ns ns ns ns ns ns ns
Before GCK rising edge Before DCK rising edge After DCK rising edge
Electrical Characteristics (VDD = 5.0 V, Ta = 25C unless otherwise noted)
CHARACTERISTIC Input Voltage "H" Level Input Voltage "L" Level Output Leakage Current Output Voltage ( SOUT) Output Current (Channel-Channel) Output Current (Chip-Chip) Supply Voltage Regulation Supply Current1 SYMBOL VIH VIL Ileak VOL VOH IOL1 IOL3 % / VDD CONDITION MIN. 0.8 VDD GND TYP. MAX. VDD 0.2 VDD 0.1 0.2 UNIT V uA V % % %/V

VOH = 17 V IOL = 2 mA IOH = -2 mA VOUT = 1.0V REXT = 2.6k VOUT = 1.0V REXT = 2.6k REXT = 3k

4.8
3 4
42.2 1
5 10
2 43.4 1.5

IDD, analog VDD=5V, REXT = 1k IDD, digital VDD=5V, Cload=2pF, DCK=GCK=1MHz
mA
1
ILED excluded.
8x3-CHANNEL CONSTANT CURRENT LED DRIVERS
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DM163
Switching Characteristics (VDD = 3.3V, Ta = 25C)
CHARACTERISTIC SOUT Rise time SOUT Fall time SOUT Propagation delay (L to H) SOUT Propagation delay (H to L) IOUT Rise time IOUT Fall time IOUT Propagation delay After GCK or EN_B (L to H / OFF to ON) IOUT Propagation delay After GCK or EN_B (H to L / ON to OFF) SYMBOL CONDITION MIN. TYP. 4 4 24 20 15 20 35 MAX. 5 5 30 25 18 25 37 UNIT ns ns ns ns ns ns ns
tor tof tpLH tpHL tor tof tpLH
VIH=VDD VIL=GND REXT=3K CL=13pF

tpHL
VIH=VDD VIL=GND REXT=3K VLED=3.3V RL=120 CL=33pF
30
35
ns
Switching Characteristics (VDD = 5.0V, Ta = 25C)
CHARACTERISTIC SOUT Rise time SOUT Fall time SOUT Propagation delay (L to H) SOUT Propagation delay (H to L) IOUT Rise time IOUT Fall time IOUT Propagation delay After GCK or EN_B (L to H / OFF to ON) IOUT Propagation delay After GCK or EN_B (H to L / ON to OFF) SYMBOL CONDITION MIN. TYP. 4 4 19 17 4 15 26 MAX. 5 6 25 23 6 18 30 UNIT ns ns ns ns ns ns ns
tor tof tpLH tpHL tor tof tpLH
VIH=VDD VIL=GND REXT=3K CL=13pF

tpHL
VIH=VDD VIL=GND REXT=3K VLED=5.0V RL=120 CL=33pF
20
25
ns
Input Capacitance (Ta = 25C)
INPUT NODE
SYMBOL CSIN CDCK CGCK CLAT_B CEN_B CRST_B CSELBK
CONDITION
MIN.
TYP.
MAX.
UNIT
SIN DCK GCK LAT_B EN_B RST_B
SELBK

3 3 3 3 3 3
3

pF pF pF pF pF pF pF
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Parameter Measurement
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Serial Shift-In Luminance Data (Shift Register Architecture)
Figure 3. Serial Shift-In Luminance Data Structure This serial shift (shift register) architecture follows a FIFO (first-in first-out) formate. The MSB (Most Significant Bit), both 8th bit and 6th bit at the 23rd channel, is the first data bit that shift into the driver. And the LSB (Least Significant Bit) data, the 1st bit at the 1st channel, is the last bit in the data sequence. Furthermore, the SELBK control signal is set to determine in which bank the data are placed.
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Timing Diagram
Figure 4. Timing diagram when 6bits are correction terms and 8bits are image terms When 6 bits are correction terms and 8 bits are image terms (as shown in Fig 4), users must set the controller signals according to below sequences: (1) Set SELBK=L (Bank 0) and begin shift in 6 bits correction data (2) Set LAT_B=H to update the correction data after all correction data are in place (3) Set SELBK=H (Bank 1) and begin shift in 8 bits image data (4) Set LAT_B=H to update image data after 8 bit image are all in place. DM163 will utilize the 8 bits image data to determine the grayscale of each channel (5) Repeat steps (3) and (4)
Figure 5. Timing diagram when both 6bits and 8bits are used as image terms
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When both 6 bits and 8 bits bank are used for images terms (As shown in Fig. 5), users should set the controller signal in accordance to the following: (1) Set SELBK=L (Bank 0) and begin shift in 6 bits correction data (2) Set SELBK=H (Bank 1) and begin shift in 8 bits image data (3) Set LAT_B=H to update image data after both 8 bit and 6 bit image data are all inplace. (4) Repeat steps (1) to (3)
Timing Diagram
Figure 6. Detailed timing diagram of data transference Figure 6 shows the detailed timing diagram of data transference. The synchronous clock DCK is designed to trigger at the positive edge. And the LAT_B triggers at the negative edge. To completely fill up both 6 bit and 8 bit shift register, a total of 336 DCK count is required (144 DCK for 6bits mode and 192 DCK for 8bits mode). Example depicted in figure 6 shows 6'b001111 data at 6bits bank and 8'b00001111 at 8bits bank respectively. Therefore, the average output current is (15/256) x (15/64) x Iout. Formula I (out, avg)= (BANK 1/256) x (BANK 0/64) x Iout, provides a useful way to calculate the input data and the output current. Iout is the reference current value shown in figure 12. Users could utilize the formula Iout =47*Vrext / Rext to get an approximate value of Iout.
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DM163
Particular Phenomenon
DM163 incorporates a different PWM counter, as described in Figure 2, hence its output waveform demonstrate a very different characteristics compare to conventional PWM counter.
(1) Nonconsecutive counter
The non-consecutive PWM counter incorporate by DM163 demonstrated a waveform pattern similar to Figure 7. Its waveform is spread-out into each PWM cycle, resulting lots of intermediate pulses during each PWM cycle. In Fig 7, if all the intermediate pulses are added up, it would equal to 50% luminance which is the same as the conventional method. By spreading out the PWM pulses, this approach can help prevent LED from flickering in lower grayscale situation.
Figure 7. An Example of Nonconsecutive PWM Signal
(2) 8+6 bits Comparator
The comparator illustrated in Fig 2 is another one of the unique designs in DM163. The comparator's output will be "H" only when value at "+" is larger then the value at "-" (in other word, comparator will be "L" when value in"+" equals to value in "-" or value in "+" is less than value in "-"). Only when both 8 bit and 6 bit comparator are "H" will there be current in the output channel. Due to this unique comparator design, DM163 exhibit a very distinct output characters in two certain scenario. In the first case, DM163 output will always be "OFF" when either one of the 8 bit or 6 bit bank is filled with 0. In 2nd scenario, when all bit value at both 8 bit and 6 bit bank are loaded "H", DM163 output will exhibit its highest luminance value (but not 100% luminance value). Due to the nature of comparators design, PWM control signal will be zero in the condition of 8bits counter=8'bFF or 6bits counter=6'b3F. Consequently, the PWM control signal will be 0 for 28+26+1 GCK rather than always high.
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Application Diagram
Figure 10. Application Diagram Note: 1. The RST_B should be connected to controller to initialize the IC. 2. VDDH_R/G/B should be connected to Vled_R/G/B respectively. The Vled_R/G/B are power supply of Red/Green/Blue LEDs. 3. VSS_DR is the ground pin of LEDs. And it could be connected to VSS.
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Application Diagram (Cont.)
Figure 11. Application Diagram of anode-common LED
Driver Output Current (VDD = 3.3V and 5.0V, Ta = 25C)
Figure 12. REXT vs. Output Current
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Driver Output Current (Cont.)
Figure 13. Vout vs. Output Current The curve shown in Fig 12 is the average result of a large number of samples. Due to chip-to-chip variation in Vrext, users may observe a different Iout-Vout curve than above. However, the curves of VDD=5v and VDD=3.3v should be close to each other when the same chip is tested because DM163 utilizes a negative feedback circuit to keep the average voltage of Vrext pins close to constant, regardless of the VDD. Therefore, the Iout-to-Rext curve should not be seriously influenced by VDD variation. The Fig 13 illustrates the relation between Vout and Iout. Iout is the constant value when Vout exceeds the voltage of turning point. In other words, Iout is independent of the fluctuation of Vout if IC is biased in this condition.
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DM163
Package Outline Dimension QFP44
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DM163
QFN40
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DM163
The products listed herein are designed for ordinary electronic applications, such as electrical appliances, audio-visual equipment, communications devices and so on. Hence, it is advisable that the devices should not be used in medical instruments, surgical implants, aerospace machinery, nuclear power control systems, disaster/crime-prevention equipment and the like. Misusing those products may directly or indirectly endanger human life, or cause injury and property loss. Silicon Touch Technology, Inc. will not take any responsibilities regarding the misusage of the products mentioned above. Anyone who purchases any products described herein with the above-mentioned intention or with such misused applications should accept full responsibility and indemnify. Silicon Touch Technology, Inc. and its distributors and all their officers and employees shall defend jointly and severally against any and all claims and litigation and all damages, cost and expenses associated with such intention and manipulation.
8x3-CHANNEL CONSTANT CURRENT LED DRIVERS
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